The contents of the original DCR994 are replaced in full by the following:
Specification is amended throughout in order to implement changes applicable to “Die Components” based on the requirements for Die Components implemented in ESCC5000 Draft 7E per DCR944 and ESCC9000 per DCR991 (with reference to the requirements for procurement of active chips in ECSS-Q-ST-60-05C Rev.1) and the current requirements for Naked Die Components in ESCC5010 issue 2.
All changes (both editorial and technical) made to ESCC 5010 issue 2 are identified (highlighted yellow) and detailed in the DCR attachment: ESCC 5010 draft 3C.
Note: Changes per DCR904 are also highlighted (green) in the DCR attachment ESCC 5010 draft 3C.
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Note:
For information & clarification purposes, the following requirements specified for die components in ECSS-Q-ST-60-05C are not applied to ESCC5010 Draft 3C per this DCR (i.e. the requirements of 5010 issue 2 are retained):
• Para 4.3.2, 4.4, 5.3.1, 9.1.2, 9.2, 9.5, 9.9, etc.: Traceability: traceability to each wafer (not just wafer lot) per 5010 issue 2 is retained as concluded by PSWG#77 (not in 5000 & 9000)
• Para 5.2.2(b), Chart F2: the High & Low Temp electrical measurements are retained during wafer screening for die components
• Para 5.3.1, 6.4.2, 8.5.1, 8.5.2 & Chart F3B: Sampling and allowed failures requirements for testing of Die Components (tested on the assembled Packaged Test Sublot samples) are not changed from ESCC5010 issue 2
i.e.: they are not defined based on the bondability & user LAT requirements specified in ECSS Q ST 60-05C Rev.1 Para 8.3 & Table 8-2.
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Changes are summarised as follows (para numbers refer to ESCC5010 draft 3C):
1) Para 2.1, 2.2 & 4.5: reference to ESCC 22600 for materials and finishes restrictions is added (ref to ECSS-Q-ST-70-02 is deleted).
2) Para 3: Definitions of ‘Die Components’ & ‘Packaged Components’ are specified.
3) Additions and modifications to existing requirements for die components & packaged components:
Spec title, Para 4.1, 4.1.5.1, 4.1.5.2, 4.3.3, 4.4, 4.5, 4.7, 5.2.2, 5.2.3, 5.3.4, 5.3.5, 6.1, 6.4, 6.4.1.1, 6.4.2.1, 6.4.2.2, 7.4, 8.1.1.1, 8.1.1.2, 8.1.2.1, 8.5.1, 8.9, 8.18, 9.1, 9.5, 10, Chart F1B, Chart F2, Charts F3A & F3B, Chart F4B :
Requirements for Die Components are amended; see attached ESCC5010 draft 3C for details.
Notes on specific amended requirements:
• Para 4.1, 7.4, 8.18, Chart F1B & F4B: 1000h LVT life test on each wafer lot for qualified Die Components is deleted (see below for justification).
Note: The procurement lot based user LAT 1000h/125°C life test and post life wire pull/shear tests of ECSS-Q-ST-60-05C Rev.1 Para 8.3.3.2.4 are not included as requirements in ESCC5010 Draft 3C on the basis that:
a) As part of ESCC qualification and maintenance of qualification, a (2000h or) 1000h life test is performed on a sample of components every 24 months (i.e. on assembled Naked Die components from a Packaged Test Sublot)(the same as for qualified Packaged components).
b) Bond pull/shear tests are performed on each lot after assembly of the Packaged Test Sublot samples plus are also performed as part of ESCC qualification and maintenance of qualification on a sample of components that have either been Screened or subjected to a 1000h life test, every 24 months.
c) The user LAT requirements of ECSS-Q-ST-60-05C Rev.1 should be performed by the hybrid Manufacturer/customer using his own assembly processes (not the die Manufacturer).
d) ESCC 5000 draft 7E per DCR944 does not include a 1000h LVT life test on each wafer lot for qualified Die Components.
• Para 5.2.2, 9.5 & Chart F2: Testing at wafer/die level applicable to Die Components is specified based on the requirements in ECSS-Q-ST-60-05C Rev.1 Para 8.3.1 (& ESCC5000 Draft 7E) but note that the High & Low Temp electrical measurements (Para 5.2.2(b)) are retained during wafer screening for die components.
• Para 6.4.1.1; Failures to high and low temperature electrical measurements do now count towards PDA3 (in order to be consistent with ESCC5000 & 9000 plus Para 6.4.2.2 of ESCC5010 for die components)
• Para 6.4.2.1, Optional high and low temp electrical measurements are added to Chart F3B to be consistent with ESCC5000 & ECSS-Q-ST-60-05C
• Para 10: an option to be able to deliver the Packaged Test Sublot samples is added.
• Chart F3A: Room Temperature Electrical Measurements prior to Burn-in 1 are retained but are made optional in order to be consistent with ESCC5000 & 9000 which do not require this test at this point during Screening Tests.
• Chart F3B: new chart has been produced specifically for Die Components in order to make the different requirements applicable to Packaged Components and Die Components clear.
Serialisation is moved to be before Room Temperature Electrical Measurements which is now read and record (not go-no-go)
An optional High and Low Temperatures Electrical Measurements is added before PDA0 (to be consistent with ESCC5000 & ECSS-Q-60-05C).
Justification:
The requirements for die components (and packaged components) already included in ESCC 5010 issue 2 are reviewed and amended to be consistent with the same requirements being implemented into ESCC 5000 & 9000 (by DCRs 944 & 991) except for specific requirements in line with conclusions made by the PSWG during their review of all 3 DCRs (944, 994, 991).
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