LoginComponent Details GH50-10 transistor process
Component |
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| EPPL Part: | 2 | |||
| Part Type: | GH50-10 transistor process | |||
| Group: | MICROCIRCUITS | Subgroup: | MICROWAVE MONOLITIC INTEGRATED CIRCUITS (MMIC) | |
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| Description: | ||||
0.5 um GaN HEMT (AlGaN/GaN on SiC substrate) for Power amplifier up to C band.MAXIMUM RATING for AB class operation** Vds (at Ids = 50 mA/mm): 60V (50V recommended)** Vgs: -7V** Output power at PAEmax +1dB** Maximum VSWR under recommended ratings: 5:1 all phases (sustained operation should stay below a recommended VSWR of 3:1 to safeguard reliability)** Ig (under DC bias only) > -0.5mA/mm** Tj (under recommended conditions): 160CNotes:1- All conditions can be fulfilled simultaneously.2- The given values must not be exceeded at the same time even momentarily for any parameter, since each parameter is independent from each other, otherwise deterioration or destruction of the device may take place.3- Recommended operating output power is defined as the input power level to operate at maximum power added efficiency (PAE)4- Junction temperature is specified as the maximum peak junction temperature NOTE: As during reliability tests a maximum power bar size of 12mm was tested (CHK040 topology), the space evaluation domain is limited to 12mm of total periphery of power bars. For sizes higher than 12mm it is the responsibility of the users to perform relevant reliability tests. |
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ESCC Specifications: |
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| Manufacturer: | ||||
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UMS Bât Charmille - Parc Silic de Villebon - Courtaboeuf, 10 avenue du Québec 91140 Villebon-sur-Yvette France |
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| Ref. number: | ||||
| 1633759568778810401 | ||||
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Approval Status
Qualification: |
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| Others | |||
| Other: | |||
| Highest screening level (MIL): | |||
| An audit of the line has been conducted at UMS Ulm in February 2012. | |||
| Evaluation programmes or other approvals: | |||
| A Relibility test campaign based on ESCC 2269010 was performed under the supervision of DGA, CNES and ESA. This test plan (300 components issued from 8 runs, 16 wafers tested, 80 000 hours of life test) was built to determine the safe operating areas of the technology (including ROR and AMR) | |||
| Former space usage: | |||
| - | |||
Previous Procurement and Test Data
Test data (Evaluation, Lot acceptance, DPA, MIL QCI/TCI, ...): |
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| Test Summary:Storage (1000h @250°C and 300°C on PCM) and storage (6000h @250°C) on 50W power bar: Ea=2.1eV, MTF=1100yearsHumidity test on TCV (85%/85°C 1000h): no failureHumidity test on DEC (85%/85°C 1000h): no failure Humidity test on 50W power bar (85%/85°C 1000h): no failure Thermal cycles on TCV (1000 x -65/+125°C): no failureThermal cycles on 50W power bar (500 x -55/+125°C): no failureHigh temperature reverse bias test on DEC V1 up to 100V of Vds, Vgs =-7V @175°C: no failure up to 3000h, some failures before 2000h at Vds=120VHigh temperature reverse bias test on DEC V3 up to 120V of Vds, Vgs=-7V @ 175°C: no failure up to 2000h, no failure up to 6000h at Vds=100V Aging tests on DEC V1 (up to 3000h and up to Tj=335°C): wear out (run away mechanism identified Ea=1.82eV)DC life-test on DEC V1 Tj=245°C Vds=50V: first failure at 3900hDC life-test on DEC V1 Tj=211°C Vds=50V: 6600h (one extrinsic failure)DC life-test on DEC V3 Tj=205°C Vds=50V: no failure up to 5997hDC life test on 40W power Tj=223°C Vds=50V: no failure up to 2580hDC step stress on DEC V1 125°C: up to Vds=100V (48h/step) no failureRF Step stress DEC V3 à 50°C (AMR): failure at Vds=60V and for compression =PAEmax+2dB RF life-test on DEC V1 at Vds=50V (2000h @ Tj=205°C): no failureRF life-test on 40W power bar at Vds=50V (1000h @ Tj=193°C): no failure | |||
Radiation Hardness Data
Total Dose Effects: |
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| As in annex | |||
| Displacement damage: | |||
| Single event effects (SEL/SEU/SET/SEFI/SEB/SEGR/others): | |||
| As in annex | |||
Remarks |
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