|
|
|
|
|
|
|
|
|
|
|
|
The changes applicable to this DCR are clarified, amended and added to as follows based on a review of this DCR performed by CNES and Manufacturers Exxelia Technologies, AVX-TPC and AVX-NI:
See attached ESCC 23400 Draft 5A that shows the changes proposed per this DCR (highlighted and commented on).
…………..
Para. 5.2: the "referee" magnification of x200 is added which is considered suitable to detect small defects such as voids in thin layers.
i.e.:
Add the following to the end of the 2nd subpara:
(upto x200 recommended)
…………..
Figure 3: A caption is added to Figure 3 as follows to clarify the mounting dimensions and details.
Note: the space between ring and capacitors is amended to be > 2mm (instead of > 3mm) based on experience that indicates > 2mm is sufficient.
Capacitors mounted parallel to one another and such that the electrode planes are perpendicular to the section/mounting plane.
Separation between capacitors > 1mm
Space between capacitors and ring > 2mm
…………..
Figure 5: Captions are added to the figure to clarify the requirements; see attached for details
…………..
Para. 6.2: New change is added to this DCR per CNES/AVX-TPC/Exxelia review of DCR965 as follows:
Add the following as the first line in Para 6.2:
Voids criteria are not applicable to ceramic chip capacitors with dielectric thickness less than 10µm.
Justification:
Voids can’t be inspected in a consistent and repeatable way when dielectric layers are very thin. The proposal is to suppress the inspection of voids when dielectric thickness is less than 10µm. For those dielectric thicknesses, porosities are not considered to be a reliability hazard.
|
|
|
Login
